1. Field of the Invention
The present invention relates to a data transmission technique for transmitting data between different clock domains.
2. Description of the Related Art
A test apparatus is employed in which a test pattern is supplied to a semiconductor device which is a device under test (which will be referred to as the “DUT” hereafter) so as to test the operation thereof, thereby judging the quality thereof. FIG. 1 is a block diagram which shows a configuration of a test apparatus.
A test apparatus 100 mounts a pattern generator (PG) 2 configured to generate a test pattern to be supplied to a DUT 200, and a timing generator (TG) 4 configured to define the timing at which the test pattern is supplied to the DUT 200.
The timing generator 4 is packaged as a combination of a logic circuit 12 and a high-precision circuit 14. In order to improve the package density, in many cases, these circuits are integrated on a single semiconductor substrate. However, the logic circuit 12 has a problem of a large amount of switching noise. Such switching noise has an effect on the high-precision circuit 14, resulting in degraded timing precision. In order to suppress such an effect, the logic circuit 12 and the high-precision circuit 14 have separate respective power supplies 1a and 1b. Furthermore, the logic circuit 12 and the high-precision circuit 14 have separate respective distribution paths for reference clocks (which will simply be referred to as the “clocks” hereafter) LREFCK and HREFCLK.
The logic circuit 12 operates in synchronization with the clock LREFCK, and transmits data that is in synchronization with the clock LREFCK to the high-precision circuit 14. The high-precision circuit 14 includes a fine delay circuit (not shown). The high-precision circuit is configured to set a delay amount according to the data received from the logic circuit 12 so as to supply data to the DUT 200 at a timing specified by the user.
The logic circuit 12 operates at the clock LREFCK, which is a relatively low-speed clock, e.g., 286 MHz. In addition, the high-precision circuit 14 uses a high-speed clock HREFCK, e.g., a 2.28 GHz clock that is obtained by multiplying the 286 MHz clock by 8. FIG. 2 is a block diagram which shows the relation between the logic circuit 12 and the high-precision circuit 14. A multiplexer 16 is arranged between the logic circuit 12 and the high-precision circuit 14. By using such a clock obtained by multiplying a given clock by N (N represents an integer), such an arrangement allows multiple logic circuits to be connected in parallel with a single high-precision circuit. Thus, such an arrangement provides an operation which is equivalent to the operation of an arrangement in which the logic circuit 12 operates at a frequency N times the frequency that is actually applied to the logic circuit 12.
The two clocks LREFCK and HREFCK are each generated using a clock obtained by a single oscillator as a reference clock, and thus although the periods of these two clocks are proportional to each other, the phases of the clocks are not necessarily consistent. Furthermore, the phase relation between these clocks fluctuates due to irregularities in the process or the like. Accordingly, in a case in which a high-speed clock is employed, such fluctuation in the phase relation approaches the period of the clock, leading to a problem in that such an arrangement does not ensure normal operation. Thus, such an arrangement requires an adjustment unit which enables the high-precision circuit 14 to receive the data output from the logic circuit 12 side with high precision.
In conventional arrangements, in order to solve such a problem, a FIFO (First In First Out) circuit is provided between the logic circuit 12 and the high-precision circuit 14. However, as the operation frequency used in the high-precision circuit 14 becomes higher, it becomes difficult to mount a complicated and large-scale logic circuit such as a FIFO. Furthermore, in a case in which a frequency multiplying circuit having a multiplication factor of N operates with a free-running clock, such an arrangement cannot set the start phase of the FIFO at a desired position, leading to a problem in that a normal operation state cannot be established.